The size of the transistors is decreasing continuously with the decrease
in the thickness of the silicon dioxide gate dielectric to increase the gate
capacitance and thereby increasing the drive current, which ultimately provides
better device performance 14. The CMOS scaling of the devices is facing challenges
due to shrinking geometries, lower supply voltage, and higher frequencies, which
have negative impact on the device by increasing short channel effect due to
which leakage (gate leakage and sub-threshold leakage) in the device is
increasing constantly. The enhancement in the scaling technology has increased the
need of low power based circuits 14. In nanometer devices, CMOS based circuit
are not used due to problem in its fundamental material, short channel effect
and high leakage 14. New technologies are needed for handling the various effects
of MOSFET technology. As the planar MOSFETs shows a significant SCE (Short
Channel Effect) and hence the designers are concentrating on FinFETs, which
have negligible SCE for the same channel length.
FinFETs have attracted increasing attention
over the past decade because of the degrading short-channel behaviour of planar
MOSFETs. In the planar MOSFET channel is horizontal, the FinFET channel (also
known as the fin) is vertical. With multiple fins and smaller fin heights leads
to more flexible and width of the channel can be increased, which in turn leads
to more silicon area.
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