66 OKI Technical ReviewOctober 2007 / Issue 211 Vol.74 No.3Development of chip stacking technology using through electrodesKatoHigher density and higher performance of LSI systemVarious mounting technologies have been developed. However, the LSI chipSince it is reaching the limit in two-dimensional mounting which arranges them side by side,A technique for stacking and mounting these in three dimensions is indispensable.
TertiaryAs an original packaging technology, a penetration formed through a semiconductor substrateThere is an electrode (Through Silicon Via: TSV), and between chipsCan be connected at the shortest distance, thereby realizing high performance, high speed operation LSIStem can be realized 1) 2) 3) 4).Against this backdrop, Elpida Memory * 1), NECElectronics * 2), OKI’s three companies, high speed and large capacityMultilayer DRAM that realizes miniaturization simultaneously (DynamicRandom Access Memory) jointly opened in 2004Is emitting 5) 6) 7). Memory stacking, mobile phones and moreIt is possible to dramatically reduce the module it is carrying,High performance can be realized by stacking and stacking LSIs.In this paper, we are working on OKI as the next generation mounting technologyThrough electrode technology applied to laminated DRAM and laminating technologyI will explain it.Figure 1 shows the development targets of the stacked DRAM. Conventional core part andAfter separating the interface section into separate chips, the through electrode8 layers of DRAM core layer with 512 Mbit capacity having TSVTo 4 Gbit DARM. And apart from the DRAM core layerThe external input / output functions are integrated on the interface chip,Thereby realizing the operation.In developing the DRAM core layer, how to form through electrodesSelection of law and materials is important for developing process technologyIt was an element.
Table 1 shows a comparison of various through electrode forming methods.As a forming method, before the DRAM element is formed, a through electrodeVia First method of forming DRAM elements after formingVia Last method for forming the electrodes, the Via Last method is classified intoProcessing from the front surface side of the substrate and processing from the back side of the substrateThere is a method. Via Last method is the process of Via First methodIt is good that there is freedom, but metal contamination and post processThere is a problem that there is a limitation on the process temperature. on the other hand,The Via First method shows that Poly-Si has higher resistance than metalThere is a problem that the filling time of the DRAM is extremely longIt is most suitable for the process. From the above, the processI decided to select the Via First method, and the issue of penetrating electricityDevelopment of polar technology, confirmation of its electrical resistance and opening of laminating technologyI made a departure.Figure 2 shows the process flow of the Via First method.
Process FuRow, (1) dry etching using SiO 2 as a hard maskEtch Si, ?CVD (Chemical VaporDeposition) to form a sidewall insulating film, (3) high Pprocess flowDevelopment of stacked DRAMVia FirstVia LastFromFront sideFromBack sideCascadedinterconnect Easy Difficult EasyTemperaturerestriction None Must be low Must be lowContamination None Sensitive SensitiveFilling materials Poly-Si Cu, W, Al Cu, AlTable 1 Comparison of various penetrating electrode forming methods* 1) Elpida Memory Co., Ltd. Technology & Development Office? 229-1197 3-1-35 Minamihashimoto Sagamihara-shi, Kanagawa Prefecture* 2) Advanced Device Development Division NEC Electronics Corporation 1120 Shimokuzawa Sagamihara, Kanagawa Prefecture 229 – 1198Figure 1 Development targets of stacked DRAMConventionalSingle Layer DRAMChip Stack DRAM WithThrough Silicon Via (TSV)8 Layers3 Gbps / pinInternalDRAM Bus TSV Core Peripherals4 Gbit DensityPeripheralsInterposerDRAM Core67 OKI Technical ReviewOctober 2007 / Issue 211 Vol.74 No.
3Device feature ?(Phosphorus) concentration Poly-Si, ? CMP (ChemicalMechanical Polishing) to remove Poly-Si on the surface,? After forming the DRAM element, micro-bumpForm the ?, ? easy to handle the substrateThe support was affixed to the front side, the substrate was backgrinding (BG)And thinned to 50 ?m with CMP, ? do not peel the supportTo form a nitride film by low temperature CVD, ? dry etchTo form a wiring by opening the penetrating electrode portion with ?, electrolytic platingForm microbumps on the back side, ? Support the support for minutesDicing away.Since the growth rate of poly-Si by CVD is very slow,It was necessary to greatly shorten the filling time. Therefore,We devised the structure of the poles. 3 shows the structure of the poly-Si through electrode, FIG. 4The surface SEM (Scanning Electron Microscope: runningElectron microscope) image. The through electrode is a 2.5 ?m Si postAre arranged at intervals of 2 ?m, for example, 20 ?m diameterThe filling time of Poly-Si is set to 1/10 from the penetrating electrode of FIG.
ToIn addition, in order to reduce the parasitic capacitance, an outer ring is placeding.FIG. 5 shows etching time and trench depth and hard massRelationship of the amount of etching etched, FIG. 6 shows after etching for 1700 seconds (a)And the cross-sectional SEM image of the Poly-Si through electrode after CMP (b).With an etching time of 1500 to 1700 seconds it is about 50 ?m deepIt was found that the Si / SiO 2 etching selection of this processThe ratio was 40 or higher, and a sufficient selectivity was obtained.Poly-Si through electrodeFigure 2 Process flow of Via First methodVia first? Via Etch?Isolation? Poly-Si? CMPDRAM Process?Front Bump? BG + CMP? Isolation?Contact? Back BumpFront side Back side? DicingSupportFig.3 Structure of Poly-Si through electrode2.
5 ?m 2 ?m 2 ?m2.5 ?m2 ?m28 ?mFig. 4 Surface SEM image of Poly-Si through electrodeFIG. 5 Etching time and trench depth andRelationship of Hard Mask Etching Amount1300 1500 1700 304050600123FourEtching time [s]Hard mask thickness change [?m]Trench depth [?m]Si / SiO 2 Selectivity> 40Fig.6 SEM image of cross section of Poly-Si through electrodeAfter 1700 seconds etching (a) and after CMP (b)52.5 ?m depth(a) After Etching (b) After CMPSiO 2 Hard Mask68 OKI Technical ReviewOctober 2007 / Issue 211 Vol.74 No.3Depending on the bonding failure of the micro bump and the load pressure at the time of bondingIn order to prevent the destruction of the lower layer wiring, the structure of the micro bumpWe optimized the bonding conditions by devising.
Fig. 7Sectional structure. Micro bumps are arranged at intervals of 50 ?m, The Sn – Ag / Cu structure on the front side and the Au / Ni structure on the back sideIt inhibited surface oxidation of Cu by making it. FIG. 8 shows a microbumpFIG. 2 shows an oblique SEM image and a cross-sectional SEM image. Micro-A flat bump (a) plated with Cu with a normal chemical solution and a flat bump (a)Convex bumps plated with Cu with a chemical containing additives for inhibitors(B) was prepared. For flat bumps, extra Sn – Ag protrudesTo the nitride film, and unnecessary parasitic capacitance is generatedIt became a factor causing it.
On the other hand, convex bumps are made of Sn – AgThere was no protrusion of the material, and a good cross-sectional state was obtained. 9An oblique SEM image of the laminated TEG (Test Element Group)FIG. The micro bump adopts a convex bump,FC (Flip Chip) bonding optimized heating temperature and load pressureBy doing so, the maximum of nine layers without Sn – Ag protrusion and cracksChip stacking was realized.In FIG. 10, the electric resistances of the 2-layer, 4-layer, and 8-layer through electrodes TEG. The measured structure is a daisy chain,A through electrode TEG chip is stacked on the interface TEG,A TEG chip for folded connection is mounted on the top layerThere. The resistance value is proportional to the number of stacked layers, and the penetrating electrode 1About 4.
1 ? was obtained per piece. This is because the 8 layer DRAMIt is a value that has no problem as a pin.Figure 11 shows the core layer layout diagram of the prototype DRAM, The sectional SEM image of the stacked prototype DRAM is shown in Fig. 12.
When observing the core layer portion of the prototype DRAM,Ensure that eight layers of chip stacking are made without cracksI acknowledged. Currently we assemble stacked prototype DRAMWe are conducting evaluation and are promoting its practical application.Laminated results of prototype DRAMElectrical resistance of through electrodeMicrobumps and laminatedFig.
7 Cross sectional structure of micro bumpPitch = 50 ?m50 ?mBack BumpAuNi SiNFront BumpCuSn – AgAlFig. 10 Electrical resistance of the 2-layer, 4-layer, 8-layer through electrode TEGCase of 8 layers with TSV(TSV = 16)0Ten20304050607080900 5 10 15 20Number of TSVResistance [ohm]y = 4.1 x4 Layers4.1 ? / TSV123FourFive6782 Layers8 LayersFig. 8 Diagonal SEM image and cross-sectional SEM image of micro bumpThe flat bump (a) and the convex bump (b)Fig.
9 Diagonal SEM image and sectional SEM image of laminated TEGBase chipTEG chip (50 ?m t) with TSV× 9 layersTSVBump69 OKI Technical ReviewOctober 2007 / Issue 211 Vol.74 No.3Device feature ?In developing a stacked DRAM, a Si postIn order to drastically reduce the filling time of Poly-Si., And the electric resistance is a value which is not problematic in the operation of the DRAMIt was possible to establish the through electrode of Via First method.Further, by devising the structure of the micro bump and setting the FC bonding condition toBy optimizing it, we realized chip stacking of up to nine layers.
Such a three-dimensional packaging technology has a high density of the system, a highIt can contribute as a technology to realize functionalizationWe will continue to put into practical use from now on. ? ?1) Tomasaka University et al .: “Chip Through-electrode Type Technology for 3-Dimensional Mounting”, DeNenso Technical Review, Vol.6 No.2, 20012) K. Takahashi et al .
: Process Integration of 3D Chip Stackwith Vertical Interconnection “in Proc. 2004 ElectronicComponents and Technology Conference (ECTC),pp. 601 – 6093) Philip Garrou: “3D Integration: A Status Report”