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 About 8086:8086 microprocessor was designed by Intel between early 1976 and mid-1978.

It is a 16 bit microprocessor (has 16 data lines) and 20 address lines. It isdesigned in such a manner that it can provide upto 1 MB storage. This is anenhanced version of 8085 microprocessor so it consists of powerful instructionset which provides tasks like multiplication and division easily. 8086 has 2 modes-1.      Maximummode: This mode is suitable for system having multi processors. 2.      Minimummode: This mode is suitable for system having single processor.

As mentioned above that 8086 is an enhanced versionof 8085 so here are some of the differences listed below Categories 8086 microprocessor 8085 microprocessor Size 16 bit 8 bit Address Bus 20 bit address bus 16 bit address bus Memory Can access upto 1MB Can access upto 64Kb Instruction Has instruction Queue Doesn’t exists Pipelining Supports pipelined structure Doesn’t supports pipelined structure Input/output Device Can address 2^16=65536 devices Can address 2^8=256 devices  Features of 8086:·        It has instruction queue which iscapable of storing 6 instruction bytes from the memory resulting in fasterprocessing·        It is a 16 bit processor having 16 bitALU, 16 bit registers, 16 bit external data bus and internal data bus resultingin faster processing.·        It uses two stages of pipelining firstis fetch and second is execute which enhances or improves the performance.·        Fetch stage can pre-fetch upto 6 bytesof instructions and stores in queue.

·        Execute stage executes instructions.·        It consists of 29000 transistors and has256 vectored interrupts.·        It is available in three versions basedon frequencies:·        8086 – 5MHz·        8086 – 8MHz·        8086 – 10MHz Architecture of 8086: The architecture comprises of two segments:-1.

     BIU (Bus Interface Unit): It generates the 20 bit physical address formemory access and fetches instruction from memory. It then transfers data toand from the memory and Input and Output devices. It supports pipelining usingthe 6 byte instruction queue.               The main componentsof the BIU are as follows: Segment registers- Code Segment register: It holds the base address for the CS and all programs are stored in this segment. Data Segment register: It holds the base address for DS. Stack Segment register: It holds the base address for the SS.

Extra Segment register: It holds the base address for the ES. Instruction Pointer: It is a 16 bit register. It holds offset of the next instructions in the CS then address of the next instruction is calculated as CS x 10H + IP after that IP is incremented after every instruction byte is fetched and at last IP gets a new value whenever a branch occurs.

·         Instruction stream byte queue: The execution unit (EU) is supposed to decode or execute an instruction. Decoding does not require the use of buses. When EU is busy in decoding and executing an instruction, the BIU fetches up to six instruction bytes for the next instructions. These bytes are called as the pre-fetched bytes and they are stored in a first in first out (FIFO) register set, which is called as a queue.