Abstract— This paper outlines the design of the Advanced Encryption Standard (AES) in VHDL. Data security in a network is very important as the data is confidential and should be made secure. Advanced Encryption Standard is a cryptography method which is to secure electronic data. It is a block cipher type algorithm that can encrypt and decrypt digital data and uses 128, 192, or 256 bits of user key. This paper implements the 128 bit standard using the VHDL, a hardware description language. The software tool used in this paper is Xilinx ISE 14.7 Project Navigator. It works on both VHDL as well as VERILOG language.KeywordsAES; VHDL; cryptography IntroductionNowadays, everyone creates and transfers large volumes of information and data across the world. Cryptography provides a method for securing and authenticating the transmission of information over insecure channels. Cryptography is a Greek word that literally means the art of writing secrets which is the study of mathematical techniques related to aspects of information security such as confidentiality, data integrity, entity authentication, and data origin authentication. It enables us to store sensitive information or transmit it across secure networks so that unauthorized persons cannot read it. The cryptography methods are classified in several ways. For theoretical purposes , they are categorized on the basis of the number of keys that are used for encryption and decryption, and further defined by their application and use. The three types of algorithms that will be discussed are:Secret Key Cryptography (SKC): An identical key is used for both encryption and decryption processPublic Key Cryptography (PKC): One key for encryption process and another for decryption process.AES is secret key Cryptography system and a recent one which replaced its predecessor DES algorithm. AES provides combination of security, performance, efficiency and flexibility. The AES encoder uses 128, 192, or 256 bits of user key to encrypt and decrypt data in blocks of 128 bits or 16 bytes. VHDL is a hardware description language short for VHSIC Hardware Description Language, where VHSIC is an abbreviation for Very High Speed Integrated Circuit. VHDL is an international approved standard, governed by the IEEE. This language is used to design the structure and behavior of digital electronic hardware and circuits, such as ASICs and FPGAs as well as conventional digital circuits. VHDL is not an information model, a database schema, a simulator, a toolset or a methodology. However, a methodology and a toolset are essential for the effective use of VHDL. Simulation and synthesis are the two main kinds of tools which operate on the VHDL language.Literature reviewS.M. Umar Talha, Mir Asif, Hammad Hussain, Ali asghar, Hadi Ameen1 presented the study of Advance Encryption standard and its encryption and decryption process with a VHDL-Xilinx behavioural model of Encryption of AES algorithm. Hrushikesh S. Deshpande, Kailash J. Karande, Altaaf O. Mulani2 planned their work on the topic Efficient implementation of AES algorithm on FPGA in VHDL using Xilinx ISE 14.1 Project Navigator. The basic study of AES and its evolution from Rijndael algorithm is being described in this paper. The four transformation techniques of AES as well as Encryption S-box and Decryption S-box are being explained in detail. Richa Sharma, Purnima Gehlot, S. R. Biradar 3 presented Study of Advanced Encryption Standard (AES) architecture, basic concepts involved in the algorithm with 128 bits. Mital Maheta5 presented the paper on Design and Simulation of AES algorithm. The RC6 algorithm is being explained and thereby implemented. In this paper the number of slices used is very less and design with minimum utilization is presented. This design offers minimum period of 13.345 ns (Maximum Frequency- 74.934MHz).DesignThe flowchart of Encryption process of AES is presented in figure below. This flowchart is generic for all AES specifications. In Encryption process the plain text is converted into cipher text which is a random illogical text. The process of encryption has different number of transformation steps applied continuously over the input data block of 128 bits, in a prescribed number of iterations, called rounds. The length of key used in encryption decides the number of rounds. In 128-bit user key there are 10 rounds and four iterations mainly the Sub Byte , Shift Rows, Mix Coloumns and Add RoundKey. Fig.1. Flowchart of Encryption ModuleThe SubBytes stepIn the SubBytes step, we replace each byte of the state with another byte depending on the key. The substitutions are usually presented as a lookup table called as Rijindael S-box. This step gives the non-linearity in the cipher. The S-box used is derived from the multiplicative inverse over Galois Field (GF)(28), known to have good non-linearity properties. The S-box is constructed by combining the inverse function with an invertible related transformation, to protect simple algebraic properties. a00a01a02a03a10a11a12a13a20a21a22a23a30a31a32a33b00b01b02b03b10b11b12b13b20b21b22b23b30b31b32b33Fig.2. The SubBytes stepThe ShiftRows step In ShiftRows step, operation is based on the rows of the state in which the bytes of each rows shifted cyclically. For Advanced Encryption Standard, the first row is not shifted. The second row is shifted by one byte to the left. The third row shifted by two bytes to the left, and the final row is shifted by three bytes. As bytes are shifted out on the left, they reappear on the right. This operation is sometimes called as rotation. The shifting pattern for the block of size 128 bits and 192 bits is same . .a00a01a02a03a11a12a13a10a22a23a20a21a33a30a31a32a00a01a02a03a10a11a12a13a20a21a22a23a30a31a32a33Fig.3. The ShiftRows stepC. The MixColumns step The MixColumns transformation, replaces each byte of a column by a function of all the bytes in the same column. In this step, matrix multiplication is done according to GF(2^8) i.e. Galois field.b00b01b02b03b10b11b12b13b20b21b22b23b30b31b32b33a00a01a02a03a10a11a12a13a20a21a22a23a30a31a32a33Fig.4. The MixColumns stepD. The AddRoundKey step : In the AddRoundKey step, the subkey is combined with the state. For each round, a subkey is derived from the main key using Rijndael’s key schedule; each subkey and state are of same size. Using bitwise XOR, the subkey is added to corresponding each bytes of the subkey with combining each byte of the state. Add Round Key is its own inverse function because the XOR function is its own inverse. Here cipher text state XOR with round key . The round keys obtained from key expansion algorithm selected in reverse order.E. AES Key Expander : From the given initial key, the key scheduler unit will expand and generate the key that will be used in every cycle. Key expansion is an important for both encryption and decryption. For AES 128, there are 10 rounds of transformation. This algorithm takes a 4-word i.e. 16 bytes key and gives output as a linear array of 44 words (176 bytes). Fig.5. Encryption round key expander algorithmSoftware toolThe software tool used in this project is Xilinx ISE 14.7 Project Navigator. It works on both VHDL as well as VERILOG language. Very high speed integrated circuit (VHSIC) hardware description language is abbreviated as VHDL. VHDL is a hardware description language that can be used to model a digital system. It has various levels of abstraction in design.Simulation resultThe simulation waveform of the design module is mentioned below. This waveform is synthesized and simulated on software XILINX ISE 14.7 Project NavigatorEncryption processFigure shows the simulation results of the Basic iterative design of Encryption. The simulation image is taken from the Xilinx 14.7 ISE simulator.Fig.6. Simulation result of AES encryptionInput Plain text : AESUser Key : 128Output Cipher Text : 4ce22266771f457b2420b533df68a8b0Minimum period: 8.794nsMaximum Frequency: 113.708MHzMinimum input arrival time before clock: 4.194nsMaximum output required time after clock: 9.832nsnsMaximum combinational path delay: 10.559nsView of FPGAFigure below shows the view of FPGA of AES encryption module. Plain text and user key is 128-bit, the output of the aes encoder is ciphertext of 128 bit. This Cipertext is random illogical text which is very hard to crack.Fig.7. FPGA view of AES encryption moduleConclusionThe Outcome is a design system offering a sufficient level of security, and as a result ensuring confidentiality, thanks to a ciphering unit. Encryption algorithm is being used by military and government over a last couple of decades for secure communication. The main purpose of encryption is to hide data from unauthorized usage. Results are compared with previous reported designs result to show efficiency. AES-128 algorithm for encryption is simulated on Xilinx ISE 14.7 simulator. The simulation waveforms of the design modules are presented. These waveforms are synthesized and simulated on software XILINX ISE 14.7 Project Navigator.VII. Future workThe AES encoder is designed and implemented in this paper using VHDL, our next task is to provide a complete module of encryption and decryption process. The Encryption and the Decryption modules can be combined together in a single chip module instead of separate chips. Future scopeEncryption algorithm is being used by military and government over a last couple of decades for secure communication. The main purpose of encryption is to hide data from unauthorized usage. In this paper, we designed a 128 bit AES algorithm both for encryption Recent trends like Internet of things (IoT) require network security because huge amount of information is vulnerable and must be made secure over the network. In future, AES algorithm is improved by use of GPUs high performance computing capability and compared with that using CPU. Further optimization in area provides better performance for high end applications. The employment of the AES encryption are suitable for a variety of applications, such as :Secure networking routers, Wireless communications,Encrypted data storage including secure Smart Cards, Secure video surveillance systems, Secure RFID Electronic financial transactions andInternet of Things(IoT) securityReferencesS.M. Umar Talha, Mir Asif, Hammad Hussain, Ali asghar, Hadi Ameen, Efficient advance encryption standard (AES) implementation on FPGA using Xilinx system generator, International Conference on Intelligent and Advanced Systems, IEEE-2016Hrushikesh S. Deshpande, Kailash J. Karande, Altaaf O. Mulani, Efficient Implementation of AES Algorithm on FPGA, International Conference on Communication and Signal Processing, IEEE-2014:Richa Sharma, Purnima Gehlot, S. R. Biradar, VHDL Implementation of AES-128, International Journal of Advances in Electronics Engineering IJAEE Volume 3, Issue 2 Stephen Brown, Zvonko Vranesic, Fundamentals of Digital Logic Design with VHDL.Mital Maheta Design and simulation of AES algorithm- Encryption using VHDL, International Journal of Engineering Development and Research Volume 2, Issue 1, 2014.