Implementation Of Controller On FPGA Computer Science Essay

In this technological promotion of FPGA ‘s there have been many waies for DSP applications where FPGA has many advantages in supplying optimum device use adaptability and high design flexibleness.

Establishing on these characteristics Mr.Sonny bui designed a accountant in VHDL cryptography, and we implemented the same accountant utilizing Xilinx ISE on a FPGA board ( Virtex-II Pro Board, FG256 ) .And we used Chipscope logic analyser to capture the logic in VHDL cryptography and expose the all internal node signals of the circuit utilizing JTAG interface.Most of our thesis work trades with effectual working and apprehension of chipscope engineering.

Contentss:

INRODUCTION

Problem statement

Purpose

Description

3.1 Xilinx ISE 8.2i

Chapter 1

1.1 Introduction: The chief focal point of Alstom is to supply Instrumentation, control and electrification of Power workss. These sort of power workss or Industries produces flue gases and other harmful susbstances.And our thesis work is involved to turn out power coevals which is helped to hygiene these flue gases. So these filtrating systems consists of power convertors which includes three chief parts Controller, Power convertor and an Observer.

In this paper, a Controller is implemented utilizing Xilinx Chipscope logic analyzer.The chief part of accountant is to compare the incoming information with a set of points and adjust the system consequently. Therefore the accountant is built as a province feedback accountant.

A/D Converter

Perceiver

Accountant

Fig 1.1 System Overview

Chapter 2

2.1 Purpose: Accountant in general has 3 parts. A Digital signal processor, FPGA circuit and Hardware. For the high degree control of the system a Digital signal processor is used and power convertor ‘s control algorithm is run by the FPGA circuit with a short sampling interval.And Hardware accountant is an other manner to utilize FPGA accountant.

The chief intent of this work is to develop the scheduling codification in order to achieve quicker computations with user restraints.

Industrial Application

convertor

FPGA

Hard-ware

Digital Signal Proce-ssor

Accountant

Fig 2.1 Model Of Controller

Chapter 3

Desription

3.1 Aim: The chief Objective is to implement accountant utilizing Xilinx ISE 8.2i on FPGA board ( VIRTEX-II Pro, xc2v100 FG256 bit ) .This study supports users how to utilize Xilinx undertaking sailing master and chipscope for different methods to execute computations on signals inside FPGA. It is a design which is to the full simulated and requires board degree testing.JTAG interface Acts of the Apostless like communicator between FPGA and PC.

And the other chief undertaking is to demo a user how to incorporate a chipscope tool into a complex design in an efficient mode to authenticate its operation.

3.2 Software:

Xilinx ISE offers analysis tools for both design Implementation and design construct. The ISE tools aid to make optimum design consequences with timing predictability and reconfiguration with greater flexibleness and size. Xilinx ISE maps the design over the available bit country. Once after bring forthing the spot file and lading it on to the kit, we have an entree to analyse the design utilizing chipscope pro analyser.

Larger silicon country, longer is the design clip and high cost. In order to extinguish these serious causes, a good seller of FPGA merchandises, XILINX introduced a new radical testing tool for big circuits.This is what we call Chipscope logic analyser which is connected to VHDL codification and implemented with the circuit under trial on the same FPGA.

3.2.1 Chipscope Organization and its Importance:

Chipscope is a complete solution for both Software and Hardware. It does n’t depends upon testbench. To capture signal samples the Integrated Logic Analyzer ( ILA ) tool is used and Integrated Bus Analyzer ( IBA ) for coachs.

ILA: This is a nucleus which allows the user to position and trigger on signals in Hardware desin. One ILA supports one clock input, 64 internal trigger signals and one external signal. Maximum data/trigger breadth is 64 spots. There is a possibility of hive awaying multiple ILA ‘s on same FPGA. Each ILA nucleus uses 32Kbits of gaining control storage for Virtex-II family.IBA nucleuss are used to supervise system coachs.

Icon: The 2nd type of nucleus is called Integrated Control nucleus ( ICON ) . Internal RAM signals are exported utilizing ICON nucleus. ILA ‘s usage a common ICON to pass on through JTAG interface with the Personal computer. And this interface is used to configure the architecture of FPGA. These nucleuss are really utile to manipulates signals straight form hardware during run clip.

The 3rd constituent is Chipscope Logic Analyzer. It has 3 characteristics:

Configuration of ILA ‘s and ICON

Transfering informations samples to the Personal computer

Analysis of stored signal samples

Each ILA information input has a node associated with tried circuit. Chipscope Logic Anlayzer has different options for exposing the gaining controls signals. The informations can be taken in any basal types like double star, denary, hexadecimal, octal or ASCII.

3.3 Hardware:

Hardware belongs to FPGA household called VIRTEX-II Prototype which is used to verify execution. And the device used is xc2v1000 and bundle is set to FG256, velocity is set to -6. The VIRTEX-II board has a parallel IV overseas telegram which is used for JTAG constellation.

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Chapter 4

4.1 Design Overview:

rst

A1_in A1_delay

A2_in A2_delay

B1_in B1_delay

B2_in B2_delay

t_in

edge_in

rst

iLN A1

r2_pos A2

r2_neg B1

r2_ref B2

T B22

iLN iLN_buf_ut

uCN r_two_pos

u0N r_two_neg

yo_2 aˆ?

aˆ?

aˆ?

aˆ?

ION UON_eight

UON r2_ref_ut

cso_n mem_IO

data_in mem_UO

rd_n min_clk

addr data_out

we_n select_signal

T

southwest t_ut

edge_ut

a-?

a-?

a-?aˆ?aˆ?

a-?

a-?

Design Of Controller

Planing of this FPGA accountant was made by Sonny Bui. The map each block is defined below as

4.1 Interface2:

This is the really first design block in this heirarchy which acts like communicating between FPGA and Digital signal processor. Valuess for ULN and ILN are provided by DSP which are stored in memory and updated whenever needed by DSP.

4.2: Conv2:

Conv2 looks for a mention value from the values stored in Interface2.

4.3: calc_cmp:

Normalizing computations of values ILN and UCN are done by the calc_cmp.

Upcoming refernce value of conv2 is compared by squaring and adding of ILN and UCN values.

4.4: FSM:

FSM evaluates the values of R2 with R2 mention values.Depending upon the comparsion the province of the system is determined.There are 4states.Each province has

Maximum and minimal time.In these instances if the clip exceeds the maximal bound the system will be asked to halt state.The physical system ‘s positive or negative electromotive force depends upon the province of the system.

4.5: TimeTest:

The duty of detecting path of timers between FSM and hold is maintained by TimeTest.

4.6: Delay:

There is a changeless care of 1Aµs between gap of 2 switches and shutting of following 2 corresponding switches where all switches are unfastened. This makes the system to scatter staying energy and prevent cutoffs.

4.2 Procedure:

Insert control and ILA cores into HDL design.

Connect coachs and internal signals

Generate Control nucleus and ILA nucleus utilizing appropriate method.

Synthesize design utilizing Xilinx design tools.

Topographic point and route the design with ILA nucleuss.

Download bitstream on to FPGA and analyse the signals utilizing chipscope.

4.3 Using Project Navigator:

Digital design logics on FPGA ‘s are largely implemented utilizing Xilinx Project Navigator. Design entry in Project sailing master has the undermentioned stairss:

4.3.1 Making a New undertaking:

1. Open Project Navigator and choice File i? New Project.

1.JPG

2. It opens as the above figure. Give the undertaking name and undertaking location. It should be noted that the undertaking location should be in difficult disc ( C ) thrust and infinites are non allowed in Project name.

3. Put the Top-Level Module Type to HDL and click Next.

4.3.2 Selecting Device belongingss and Design flow:

1. Choose the Device belongingss like below. And simulator can be choosen as per available like modelsim or ISE simulator. Here in this undertaking we use ISE Simulator ( VHDL/Verilog ) 2.Select Following to finish this measure.

2.JPG

4.3.3 Adding beginning files or new beginnings:

1.Now select Project i? Add beginning alternatively of Add transcript of beginning.Navigate to the booklet where you stored VHDL files ( accountant & A ; sub-files ) .Project Navigator will maintain hierarchy of files demoing which faculties are instantiated to exceed faculty.

2. If something goes incorrect with synthesising design so there shows some message in console and even shows ‘ ? ‘ following to the faculty which are losing.

3.JPG

3.Hierarchy looks something like above figure in Sources window under top faculty.

4.3.4 Adding Chipscope Definition and Connection File.

1. Now right chink on the top faculty ( accountant ) of design which ought to be verified and choice New Source. Then choice Chipscope Definition and Connection File and give some appropriate name to it.

4.JPG

Click on Next to complete adding this file.

6-l.JPG

2. In order to place easy and preferable signal names under each ILA, right chink on Synthesize-XST belongingss. And choice Keep Hierarchyi? ‘Yes ‘ or ‘Soft ‘ .

3. Click on Apply and OK to complete this measure.

4. Double chink on the Chipscope Definition and Connection beginning File which intends to open Chipscope pro nucleus inserter.

8.JPG