System-on-Chip design is an integrating of multi million transistors in a individual bit for relieving clip to market and cut downing the cost of the design. Design reuse – the usage of pre-designed and pre-verified nucleuss is now the basis of SOC design.
It uses reclaimable Intellectual belongings ( IP ) blocks that supports stopper and play integrating and in bend allows immense french friess to be designed at an acceptable cost, and quality. Hence to increase the productiveness with decrease in design clip a standard interface coach protocol is required to execute the stopper and drama integrating. Open nucleus SOC design methodological analysis utilizes WISHBONE coach interface to further design reuse by relieving system-on-chip integrating jobs. In this paper we present the assorted characteristics of WISHBONE coach interface.
Two types of systems have been designed which utilizes DMA maestro nucleuss and memory slave nucleuss utilizing WISHBONE point-to-point and shared coach interconnectedness strategies and the concluding executions have been done in XILINX FPGA platform. The functionality of the system is verified utilizing Xilinx simulation consequences every bit good as board degree ChipScope Pro consequences.Index Terms-SOC, WISHBONE, Point-to-Point, Shared Bus interconnectedness, Xilinx, FPGA.
IntroductionRecent promotion in engineering allows integrating of logic maps of multimillion transistors into a individual bit. In order to maintain gait with the degrees of integrating, design applied scientists have developed new methodological analysiss and techniques to pull off the increased complexness in these big french friess [ 1 ] . System-on-Chip ( SOC ) design is proposed as an drawn-out methodological analysis to this job where rational belongings ( IP ) nucleuss of embedded processors, memory blocks, interface blocks, and parallel blocks are combined on a individual bit aiming a specific application. [ 2 ] .By and large, the IP nucleuss are developed independently from each other and are tied together and tested by a 3rd party system planimeter [ 3 ] . This required the creative activity of usage gum logic to link each of the nucleuss together. By following a standard interconnectedness strategy, the nucleuss can be integrated more rapidly and easy by the terminal user.
The WISHBONE [ 3 ] System-on-Chip ( SOC ) Interconnection is a method for linking IP cores together to organize incorporate circuits. Open core [ 4 ] SOC design methodological analysis utilizes WISHBONE coach interface to further design reuse by relieving system-on-chip integrating jobs. With usage of this standardize coach interface it is much easier to link the nucleuss, and hence much easier to make a custom System-on-Chip. The nonsubjective behind WISHBONE is to make a portable interface that supports both FPGA and ASIC that is independent of the semiconducting material engineering and can be written utilizing any hardware description linguistic communication such as VHDL and VERILOGA® [ 3 ] .This paper describes the assorted issues related to system design utilizing WISHBONE coach interface, its execution in FPGA. It besides evaluates the public presentation of the designed in footings of lower limit size and maximal velocity of the system.
The remainder of this paper is compiled as follows. A brief background of Wishbone interface rudimentss is discussed in subdivision II. Proposed system architectures are presented in subdivision III. System integrating issues are discussed in subdivision IV. Confirmation consequences are presented in subdivision V. FPGA execution of the system is demonstrated in subdivision VI.
Board flat confirmation of the design utilizing Xilinx ChipScope Pro tool is presented in subdivision VII. Finally a decision is drawn in subdivision VIII.WISHBONE BasicssThis subdivision presents a brief background of WISHBONE coach interface and its specifications. WISHBONE utilizes “ Master ” and “ Slave ” architectures which are connected to each other through an interface called “ Intercon ” . Master is an IP nucleus that initiates the informations dealing to the Slave IP nucleus. Maestro starts dealing supplying an reference and command signal to Slave. Slave in bend responds to the informations dealing with the Maestro with the specified reference scope. The Intercon is the medium consists of wires and logics which help in informations transportation between Master and Slave.
The interconnectedness can be described utilizing hardware description linguistic communications like VHDL and VerilogA® , and the system planimeter can modify the interconnectedness harmonizing to the demand of the design. This makes WISHBONE interface different from traditional personal computer coachs. WISHBONE interface supports variable interconnectedness. Master and Slave interface may utilize four types of interconnectednesss such as, point to indicate, dataflow, shared coach and crossbar switch interconnectedness [ 3 ] .The point-to-point interconnectedness is the simplest 1 that allows a individual Master interface to link to a slave interface. The dataflow interconnectedness is needed for consecutive informations processing. In the shared coach interconnectedness two or more Masters can be connected with one or more Slaves.
An supreme authority is used to let the maestro to derive entree to the shared coach. Crossbar switch interconnectedness allows two or more WISHBONE Masterss to entree two or more slaves at the same clip. More than one maestro can utilize the interconnectedness every bit long as two Masterss do n’t entree the same slave at the same clip. WISHBONE supports all the popular informations transportation coach protocols such as individual Read/Write, block Read/Write and Read- Modify-Write ( RMW ) . Large Endian and Small Endian informations telling are besides supported by WISHBONE [ 3 ] .Other coach protocols available in market are AMBA [ 5 ] , OPB [ 6 ] , and Core Connect [ 7 ] . Wishbone offers about free royalty, therefore cut downing the overall cost of the system design. WISHBONE Intercon can be designed to run over an infinite frequence scope.
This is called as variable clip specification [ 3 ] . The velocity of the operation is merely limited by the engineering of the integrated circuits.Proposed system architectures
Figure.1 shows the architecture of system design utilizing point-to-point interconnectedness that includes SYSCON, DMA and MEMORY Cores.
DMA transportations informations to and from the memory utilizing block transportation rhythms. These nucleuss are available in the WISHBONE public sphere library for VHDL [ 7 ] .The DMA nucleus is a simple 32-bit DMA unit with a WISHBONE maestro interface. Two methods of informations transportations are supported such as, individual Read/Write rhythms and block Read/Write rhythms. The type of rhythm is selected by a non-WISHBONE signal input DMODE. If DMODE input is negated, the DMA generates individual read/write rhythms, if it is asserted the DMA generates block read/write rhythms.
In block read/write manner, the DMA novices eight stages of block write rhythm, and so DMA generates a similar sort of block read rhythm.The Memory is a simple, 8×32-bit size memory faculty with WISHBONE Slave interface designed for Xilinx [ 20 ] FPGA. It consists of a negligee that interfaces the Xilinx random-access memory to a WISHBONE Slave interface. Xilinx Core Generator [ 9 ] tool is used to make the ram component.
Xilinx Core Generator is a parametric nucleus generator that generates optimized nucleus for Xilinx FPGA. It supports individual Read/Write, block Read/Write and RMW rhythms.The SYSCON besides called as system accountant is used to bring forth WISHBONE compatible clock and reset signals for the system. The clock end product is fed straight from an external clock signal called EXTCLK. The reset generator produces a individual reset signal RST in conformity with the WISHBONE reset timing.RST_ICLK_IADR_O ( )DAT_I ( )DAT_O ( )WE_OSEL_O ( )STB_OACK_ICYC_ORST_ICLK_IADR_O ( )DAT_I ( )DAT_O ( )WE_OSEL_O ( )STB_OACK_ICYC_OSysconWISHBONE Slave-MemoryWISHBONE Master-DMAFigure.1 Proposed Point-to-Point System Architecture
2 shows the architecture of system design utilizing WISHBONE shared bus interconnectedness strategy. It consists of four DMA Masters, four Memory Slaves, and SYSCON nucleuss as described above. The nucleuss are connected to each other through WISHBONE interface with a shared coach interconnectedness strategy. An supreme authority nucleus is used to allow the entree of the coach to a maestro.The ARB supreme authority is a four degree, round-robin supreme authority. An supreme authority is used in shared coach interconnectedness to allow the entree of the coach to a Master.
Round-robin grants the entree to bus on a rotating footing like a rotary switch.TungstenISecondHydrogenBacillusOxygenNitrogenTocopherolBacillusUracilSecond& A ; ARoentgenBacillusMemorySlave0MemorySlave1MemorySlave2MemorySlave3DMAMaster0DMAMaster1DMAMaster2DMAMaster3Figure.2 Proposed Shared Bus System ArchitectureSystem Integration issuesPoint-to-point interconnectedness design is a direct connexion of the maestro nucleus with a slave nucleus and is simple to plan. But the system design utilizing shared bus interconnectedness strategy is much more complex and imposes design complexnesss to the system planimeter during SOC integrating. The of import factor in planing a system is to how to travel the information around the system. The information may be a binary reference value or a simple information value. Hence coachs are used to travel the information around a system. Use of multiplexor based coach reduces the figure of pins on a bit, but it requires two clock pulsations to travel the information and reference information in a system, and therefore reduces the public presentation of the system.
To implement logic interconnectednesss multiplexor logic interconnectedness is largely used, as these are easier to route in FPGA and ASIC devices than that of three-state logic interconnectedness. Round-robin supreme authority is used to allow the entree of the coach to the Masterss. All the Masters in round-robin supreme authority are granted the coach on an equal footing. Every Slave in an interconnectedness is defined by a specific binary reference. In order to entree the Slave the Master has to decrypt the corresponding reference. Two types of methods are used to decrypt the reference in a system. These are, full reference decryption, and partial reference decrypting. In partial decrypting a scope of the reference is assigned as a decrypting reference of the Slave faculty.
In full reference decrypting full reference of the coach is utilised to entree a Slave. As portion of an reference is in usage, the size of the decipherer is minimized and it allows high velocity decipherers and speeds up the interface. As WISHBONE is utilizing partial decryption technique, the planimeter has flexibleness in specifying the reference map of the system.
Table. IADDRESS MAP OF INTERCONNECTION TOPOLOGY
Master0Slave00x00 – 0x07Master1Slave10x08 – 0x0FMaster2Slave20x10 – 0x17Master3Slave30x18 – 0x1FSing these issues VHDL top faculty files are created for both the interconnectednesss. For implementing shared bus interconnectedness topology a multiplexor interconnectednesss and non-multiplexed reference and information coachs are chosen. Table-I shows the reference map for planing the shared coach interconnectedness.Confirmation RESULTSThe confirmation of the proposed system architectures were done utilizing Xilinx ISE simulator. The point-to-point interconnectedness consequence is shown in Figure.3 demonstrates that DMA is reading and composing 01234567 informations continuously to and from the memory. Figure.
4 shows that ab initio arbiter grants request to Master1. As write signal ‘ewe ‘ is high, DMA starts composing informations from the reference 5’h08. It continues 8 stages of write operation and compose 32’hA5A5A5A1 in the informations write end product coach ‘edwr ‘ . Then it makes its rhythm end product ‘ecyc ‘ low bespeaking supreme authority to re-arbitrate. The Maestro grants the entree to the following Maestro in the round-robin i.
e. , Master2. Master2 performs 8 stages of write signal and write 32’hA5A5A5A2 to the ‘edwr ‘ coach. After Master2 leaves the coach Master3 additions the entree of coach and performs a block write operation as defined in the design and writes 32’hA5A5A5A3 to the end product coach.
Finally, Master0 is in the cringle to acquire the entree of the coach and to compose informations value 32’hA5A5A50 to ‘edwr ‘ coach.Figure.3: Simulation Consequences of Point-to-Point Architecture utilizing ISE SimulatorFigure.4: Simulation Consequences of Shared Bus Architecture utilizing ISE SimulatorThe simulation consequences show that the system interconnectedness maps accurately. It is besides clearly seeable that all the slaves are accessed by their corresponding reference values defined in the reference map.System Implementation in FPGAThe system executions of two types of architectures were done in two types of XILINX FPGA: Spartan3e and Virtex-II Pro. For memory execution Xilinx distributed RAMs are chosen. Table-II and Table-III shows the point-to-point and shared coach system execution consequences in two types of FPGAs.
Xilinx ISE 9.1 package is used as execution environment. The consequences show the point-to-point system design utilizes 40 pieces and shared coach system utilizes 292 pieces in Spartan-3e and Virtex-II Pro FPGAs. The maximal velocities of the enforced systems are listed in the tabular arraies.TABLE-IIPOINT-TO-POINT SYSTEM IMPLEMENTATION RESULTS
( Spartan3e )
( Virtex-II Pro )
No. of Slices4040No. of Slice Flip Flops6969No.
of 4 input LUTs1515Max Speed248.675 MHz450.113 MHzTABLE-IIISHARED BUS SYSTEM IMPLEMENTATION RESULTS
( Spartan3e )
( Virtex-II Pro )
No. of Slices292295No. of Slice Flip Flops416416No. of 4 input LUTs459472Max Speed118.312 MHz219.896 MHzFigure.
5: Board Level Verification Results of Point-to-Point Architecture utilizing ChipScope ProFigure.6: Board Level Verification Results of Shared coach Architecture utilizing ChipScope ProBoard degree confirmation utilizing ChipScope ProThe board degree confirmation of the system architectures have been done utilizing XILINX ChipScope Pro [ 9 ] tool and the consequences are shown in the Figure 5 and 6. Figure.5 shows in the point-to-point system DMA is continuously write and read a informations 0123456 to and from the memory. Figure.6 shows Master0 petitions for the coach by asseverating ECYC_OBUF signal.
Arbiter first grants the entree of coach to Master0. Master0 generates eight stages of block write and read signals and read and writes to and from memory a information of 32’hA5A5A5A0. The supreme authority grant signals, WISHBONE acknowledge, rhythm, stroboscope and write signals are shown in the Figure.6.
The information read and compose by Master1, Master2 and Master3 are 32’hA5A5A5A1, 32’hA5A5A5A2, and 32 ‘ hA5A5A5A3 severally.Summary and decisionsA 32-bit point-to-point and shared bus interconnectedness systems are designed and related issues were discussed. The confirmation of the design is done utilizing XILINX ISE simulator. Finally, by utilizing ChipScope Pro provided by Xilinx the proper functionality of the designed systems are observed. The undermentioned decisions are made from the above treatments: The minimal size requires for implementing point-to-point interconnectedness system is 40 pieces and shared coach interconnectedness system is 292 pieces. WISHBONE interface requires a really small logic operating expense to implement the full interface and gives rise to a extremely portable system design that works with standard logic primitives available in most of the FPGA and ASIC devices. Both the interconnectednesss support an operating frequence of more than 100 MHz.
It is besides observed that the maximal operating frequence of the design depends on the mark device engineering.For high velocity FPGA like Virtex-II Pro the frequence is higher than the low velocity FPGA Spartan3e. Hence, it supports variable clocking specification. Low cost, portable and clip to market SOC can be designed successfully utilizing WISHBONE coach interface.RecognitionThis work was supported by Ministry of Communication and Information Technology ( MCIT ) , Government of India. Besides, CAD tools and boards used in this work are supported by MCIT.